This application claims priority from Japanese Patent Office Application No. 11-293628, filed Oct. 15, 1999, which is hereby incorporated herein by reference in its entirety.
The present invention relates to a FIFO (First-in First-out) memory device and a FIFO control method.
FIG. 10 shows an example of a FIFO memory device 110. FIG. 9(b) shows an example of a memory 100 used for the FIFO memory device 110. FIG. 9(a) shows a conceptual view of a general memory 100. A control signal shown in FIG. 9(a) indicates write of data into the memory 100 or readout of data from the memory 100. An address signal indicates an address of the memory 100 to write data or to read data. When writing, the control signal indicates a write operation to write data to the address specified by the address signal. When reading, the control signal indicates a readout operation to read data from the address specified by the address signal.
FIG. 9(b) is a block diagram showing an example of the structure of the memory 100 employed for the FIFO memory device 110. The memory 100 comprises a FIFO memory array 102 and a memory control section 104. The FIFO memory array 102 is divided into m subarrays (memory rows) from [1] to [m], which are indicated by FIFO[1] to FIFO[m]. In FIG. 9(b), when input-output data, for example, has an 8-bit data width, 8-bit data (1 byte) is stored in each of the subarrays (FIFO[1], FIFO[2], . . . FIFO[m]). The memory control section 104 controls the write of data to the memory array 102 and the readout of data from the memory array 102.
Signal WD[i](i=1, 2, . . . , m) corresponds to a combination of the control signal and address signal in FIG. 9(a), which indicates write of data (DATA_W) to FIFO[i]. When the signal WD[i] is inputted to the memory control section 104, input data (DATA_W) is written to FIFO[i] of the memory array 102. FIFO_IN[i] shown in FIG. 9(b) represents the write of data to FIFO[i] of the memory array 102. Signal RD[j](j=1, 2, . . . , m) corresponds to a combination of the control signal and address signal shown in FIG. 9(a), which instructs to read data from FIFO[j]. When the signal RD[j] is inputted to the memory control section 104, the data is read from FIFO[j] in the memory array 102 to be outputted (DATA_R). FIFO_OUT[j] shown in FIG. 9(b) represents the readout of data from FIFO[j] in the memory array 102.
FIG. 10 is an example of the FIFO memory device 110 using the memory 100 shown in FIG. 9(b). The FIFO memory device 110 comprises the memory 100 and the FIFO control section 112. The FIFO control section 112 comprises an input control section 120, a write pointer register 122, an output control section 124, and a read pointer register 126. An address to write data is stored in the write pointer register 122. An address to read data is stored in the read pointer register 126. The input control section 120 controls data input (FIFO_IN[i]) and the write pointer (PT_W). The output control section 124 controls data output (FIFO_OUT[j]) and the read pointer (PT_R).
When input data and an input request are inputted to the input control section 120, the input control section 120 sends an instruction for writing (WD[i]) and the input data (DATA_W) to the memory control section 104, referring to the write pointer (PT_W). In the write pointer (PT_W), a subarray number [i] corresponding to FIFO[j] is stored. The FIFO control section 112 controls the input control section 120 and the output control section 124. For example, when an input request and an output request occur at the same time, the FIFO control section 112 allows the output control section 124 to carry out output processing after allowing the input control section 120 to carry out input processing.
FIG. 11(a) is a conceptual view showing the write pointer (PT_W) and data input (FIFO_IN[i]), read pointer (PT_R) and data output (FIFO_OUT[j]). When inputting data, the data is written to FIFO[i] specified by the write pointer (PT_W). Then, as shown in FIG. 11(b), the input control section 120 controls so that the writer pointer (PT_W) may specify FIFO[ixe2x88x921] to write data next. The initial value of the write pointer (PT_W), for example, may be set to xe2x80x9cmxe2x80x9d. In this case, the input data is sequentially stored from FIFO[m] to FIFO[1].
When outputting data, the data is read from FIFO[j] specified by the read pointer (PT_R). After that, as shown in FIG. 11(c), the output control section 124 controls so that FIFO[jxe2x88x921] may be specified by the read pointer (PT_R) to be read next. When the initial value of the write pointer (PT_W) is set to xe2x80x9cmxe2x80x9d, since data is written from FIFO[m], the initial value of the read pointer (PT_R) is set to xe2x80x9cmxe2x80x9d. Data written from FIFO[m] is sequentially read from FIFO[m] to FIFO[1].
As described above, the inputted data is stored in the memory 100 and the data is outputted in order of the data inputting. When reading or writing has been carried out in FIFO[1], the pointer (PT_W, PT_R) is changed to specify FIFO[m]. In this FIFO memory device 110, data input and data output are specified by the write pointer (PT_W) and the read pointer (PT_R), and the pointers (PT_W, PT_R) alone are changed without moving the data (FIFO[k]), even if access to the memory 100 is performed.
When these FIFO memory devices 110 are employed for full duplex communication where transmission and receipt of data is implemented simultaneously, two FIFO memory devices such as a transmitting FIFO and a receiving FIFO are generally prepared. If one of the FIFO devices overruns or overflows, the whole FIFO devices come to overrun state even if the other FIFO device is empty because these two FIFO memory devices independently operate each other. In this case, the empty FIFO device is not utilized at all.
A FIFO memory device which is capable of switching the storage capacity ratio between a transmitting FIFO and a receiving FIFO to a predetermined ratio is disclosed as means for solving such a problem in Japanese Patent Publication No. 10-285223. With the use of this FIFO memory device, for example, when receipt of input is carried out more frequently, it is possible to switch the storage capacity ratio between the transmitting FIFO and the receiving FIFO from 1:1 to 3:7. However, since the ratio is fixed, if the receiving FIFO (70% of the total storage capacity) overflows, it will come to overrun, even if the transmitting FIFO (30% of the total storage capacity) is empty. In this case, the transmitting FIFO (30% of the total storage capacity) is not utilized at all.
It is an object of the present invention to integrate two FIFOs such as a transmitting FIFO and a receiving FIFO into one FIFO, thereby effectively utilizing a memory area.
A FIFO memory device according to the present invention comprises a first input section for inputting first data, a second input section for inputting second data, a memory for storing the first data inputted from the first input section and the second data inputted from the second input section, a first output section for outputting the first data read from the memory, a second output section for outputting the second data read from the memory, a first FIFO control section for writing the first data inputted from the first input section into the memory, reading the first data written in the memory in order of the data inputting, and outputting the first data to the first output section, and a second FIFO control section for writing the second data inputted from the second input section into the memory, reading the second data written to the memory in order of the data inputting, and outputting the second data to the second output section.
A FIFO control method according to the present invention comprises the steps of writing the first data inputted from the first input section to the memory, reading the first data written from the first input section to the memory in order of the data inputting and outputting the first data to the first output section, writing the second data inputted from the second input section to the memory, and reading the second data written from the second input section to the memory in order of the data inputting and outputting the second data to the second output section.